National Semiconductor ADC12DC080CISQE
| Quantity | Unit Price | Total Price |
|---|---|---|
| 1 | $82.32 | $82.32 |
| 15+ | $18.93 | $283.95 |
| 25+ | $18.52 | $463.00 |
| 50+ | $17.49 | $874.50 |
| 100+ | $15.44 | $1,544.00 |
| N+ | $3.09 | Price Inquiry |
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| Product attributes | Property Value |
| Manufacturer | National Semiconductor |
| Product Series | |
| Packaging | Bulk | |
| Number of Bits | 12 |
| Sampling Rate (Per Second) | 80M |
| Number of Inputs | 2 |
| Input Type | Differential |
| Data Interface | Parallel |
| Configuration | S/H-ADC |
| Ratio - S/H:ADC | 1:2 |
| Number of A/D Converters | 2 |
| Architecture | Pipelined |
| Reference Type | External, Internal |
| Voltage - Supply, Analog | 2.7V ~ 3.6V |
| Voltage - Supply, Digital | 2.4V ~ 3.6V |
| Features | Simultaneous Sampling |
| Operating Temperature | -40°C ~ 85°C |
| Mounting Type | Surface Mount |
| Grade | - |
| Qualification | - |
| Package / Case | 60-WFQFN Exposed Pad |
| Supplier Device Package | 60-WQFN (9x9) |
The ADC12DC080CISQE from National Semiconductor is a dual-channel, 12-bit analog-to-digital converter with a sampling rate of 80 MSPS per channel. It features a parallel output interface and a sample-and-hold architecture. Housed in a 60-pin WFQFN package with exposed pad, it operates from -40°C to 85°C and supports external or internal voltage reference. This dual ADC is optimized for applications requiring simultaneous sampling of two signals, such as I/Q demodulation and diversity receivers.
- True Dual-Channel Simultaneous Sampling: Ensures phase-matched acquisition of two signals, critical for I/Q and diversity applications.
- 80 MSPS per Channel: High-speed conversion for wideband signals while maintaining 12-bit accuracy.
- Parallel Output: Simple, high-throughput interface compatible with DSPs and FPGAs.
- Compact 60-Pin WFQFN: Integrates two ADCs in one package, saving PCB area and reducing component count.
- Industrial Temperature Range: Reliable from -40°C to 85°C for demanding environments.
I/Q Demodulation in Communications
The dual-channel ADC12DC080CISQE is perfect for I/Q (in-phase/quadrature) demodulation in QAM receivers, sampling both components simultaneously at 80 MSPS to maintain phase coherence.
Diversity Receivers
In MIMO and diversity antenna systems, this ADC digitizes two independent RF paths concurrently, enabling advanced combining algorithms for improved signal quality.
Medical Imaging (Ultrasound)
Ultrasound systems require multiple channels for phased-array transducers. This dual ADC reduces board space while providing synchronized sampling for beamforming.
Radar Signal Processing
For monopulse radar, two channels capture sum and difference signals simultaneously, preserving phase and amplitude relationships for accurate target tracking.
High-Speed Data Acquisition Cards
In PCIe DAQ cards, the dual-channel design allows simultaneous sampling of two analog inputs, ideal for vibration analysis or power monitoring.
Test Equipment (Dual-Channel Scopes)
Digital oscilloscopes benefit from dual 12-bit ADCs at 80 MSPS, offering higher resolution than traditional 8-bit scopes for detailed waveform analysis.
- Q: What is the resolution of the ADC12DC080CISQE?
- A: It is a 12-bit dual-channel analog-to-digital converter.
- Q: What is the sampling rate per channel?
- A: Each channel samples at up to 80M SPS (80 MSPS).
- Q: How many channels does this ADC have?
- A: It has 2 input channels.
- Q: What interface does it use?
- A: It uses a parallel digital output interface.
- Q: What is the architecture?
- A: It uses a sample-and-hold (S/H) architecture, typical for high-speed ADCs.
- Q: What package is available?
- A: It comes in a 60-pin WFQFN package with exposed pad.
ADC12DC080CISQE.pdf
- Q: What is the resolution of the ADC12DC080CISQE?
- A: It is a 12-bit dual-channel analog-to-digital converter.
- Q: What is the sampling rate per channel?
- A: Each channel samples at up to 80M SPS (80 MSPS).
- Q: How many channels does this ADC have?
- A: It has 2 input channels.
- Q: What interface does it use?
- A: It uses a parallel digital output interface.
- Q: What is the architecture?
- A: It uses a sample-and-hold (S/H) architecture, typical for high-speed ADCs.
- Q: What package is available?
- A: It comes in a 60-pin WFQFN package with exposed pad.
