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Product attributes Property Value
Manufacturer National Semiconductor
Product Series ADC12V170
Packaging Bulk |
Number of Bits 12
Sampling Rate (Per Second) 170M
Number of Inputs 1
Input Type Differential
Data Interface LVDS - Parallel
Configuration S/H-ADC
Ratio - S/H:ADC 1:1
Number of A/D Converters 1
Architecture Pipelined
Reference Type External, Internal
Voltage - Supply, Analog 3V ~ 3.6V
Voltage - Supply, Digital 1.6V ~ 3.6V
Features -
Operating Temperature -40°C ~ 85°C
Mounting Type Surface Mount
Grade -
Qualification -
Package / Case 48-WFQFN Exposed Pad
Supplier Device Package 48-WQFN (7x7)

The ADC12V170CISQ from National Semiconductor is a high-speed 12-bit analog-to-digital converter with a maximum sampling rate of 170 MSPS. It features a single input channel and offers both LVDS and parallel output interfaces for flexible system integration. Housed in a 48-pin WFQFN package with exposed pad, it operates over -40°C to 85°C and supports external or internal voltage reference. This ADC is designed for high-bandwidth applications such as communications, radar, and medical imaging.

  • Ultra-Fast 170 MSPS Sampling: Captures high-frequency signals with excellent time resolution, essential for wideband applications.
  • Dual LVDS/Parallel Output: Provides design flexibility—LVDS for high-speed digital backplanes, parallel for simpler MCU interfaces.
  • 12-Bit Resolution: Balances speed and accuracy, suitable for systems requiring good dynamic range without excessive data rates.
  • Wide Temperature Range: Reliable operation from -40°C to 85°C for industrial and automotive environments.
  • Compact WFQFN Package: Exposed pad enhances thermal dissipation, enabling sustained high-speed operation.

High-Speed Data Acquisition

The ADC12V170CISQ's 170 MSPS sampling rate and 12-bit resolution make it ideal for digitizing wideband signals in oscilloscopes and spectrum analyzers, capturing fast transients with good fidelity.

Software-Defined Radio (SDR)

In SDR receivers, this ADC digitizes IF or RF signals directly, enabling flexible digital signal processing. The LVDS interface reduces noise and supports high-speed data transfer to FPGAs.

Medical Ultrasound Imaging

High-speed conversion is critical for beamforming in ultrasound systems. The 12-bit resolution and 170 MSPS rate allow precise echo signal capture, improving image quality.

Radar and LIDAR Systems

For pulsed radar and LIDAR, the ADC12V170CISQ digitizes return signals with high temporal resolution, enabling accurate range and velocity measurements.

Communications Infrastructure

In base stations and microwave links, this ADC supports direct conversion architectures, reducing component count and improving signal integrity in high-bandwidth channels.

High-Energy Physics Instrumentation

Particle detectors require fast, precise digitization of sensor pulses. The 170 MSPS sampling rate and wide temperature range make it suitable for such demanding environments.

Q: What is the resolution of the ADC12V170CISQ?
A: It is a 12-bit analog-to-digital converter.
Q: What is the maximum sampling rate?
A: The sampling rate is 170M SPS (170 MSPS).
Q: How many channels does this ADC have?
A: It has a single input channel.
Q: What interface does the ADC12V170CISQ use?
A: It supports both LVDS and Parallel output interfaces.
Q: What is the architecture of this ADC?
A: It uses a sample-and-hold (S/H) architecture, typical of high-speed pipeline ADCs.
Q: What package is available?
A: It comes in a 48-pin WFQFN package with exposed pad.
Base Product Number : ADC12V170
12-bit 170 MSPS ADC ADC12V170 Analog-to-Digital Converter LVDS National Semiconductor Parallel WFQFN-48
Q: What is the resolution of the ADC12V170CISQ?
A: It is a 12-bit analog-to-digital converter.
Q: What is the maximum sampling rate?
A: The sampling rate is 170M SPS (170 MSPS).
Q: How many channels does this ADC have?
A: It has a single input channel.
Q: What interface does the ADC12V170CISQ use?
A: It supports both LVDS and Parallel output interfaces.
Q: What is the architecture of this ADC?
A: It uses a sample-and-hold (S/H) architecture, typical of high-speed pipeline ADCs.
Q: What package is available?
A: It comes in a 48-pin WFQFN package with exposed pad.