XCZU47DR-2FFVG1517I
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Dhs. 11,605.13
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Dhs. 12,215.94
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Dhs. 11,605.13
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| 1 | Dhs. 11,605.13 | Dhs. 11,605.13 |
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| 25+ | Dhs. 10,994.35 | Dhs. 274,858.75 |
| 50+ | Dhs. 10,383.55 | Dhs. 519,177.50 |
| 100+ | Dhs. 9,161.96 | Dhs. 916,196.00 |
| N+ | Dhs. 1,832.39 | Price Inquiry |
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Zynq™ UltraScale+™ RFSoC Product Selection Guide
If you're checking out Zynq RFSoC, you're probably working on something pretty cool — maybe next-level 5G, a radar that sees farther than most, or test gear that captures signals others can't even touch.
What makes this chip so special
It packs multi-gigasample RF converters (ADCs & DACs), powerful programmable logic, and a solid Arm processor — all into one single chip.
That lets you skip most of the traditional analog front-end mess, shrink your board size a lot, cut power consumption, lower cost, and get your product to market much faster.
The three generations — quick breakdown
- Gen 1 — 12-bit converters, great value. Ideal when you want real RF performance without spending too much (good for entry/mid-level wireless or test projects).
- Gen 2 — 14-bit converters, higher sampling rates (up to 5 GSPS ADCs, 9.85–10 GSPS DACs), more channels, and SD-FEC options on some parts. This is what most people pick today for serious 5G, radar and EW work — best balance of performance and price.
- Gen 3 (with integrated DFE hard IP) — Built for cutting-edge wireless. Comes with dedicated hardware for channel filtering, CFR, DPD, complex equalizers, PQ resampling, and more. Highest RF input bandwidth (up to 7.125 GHz). Perfect if you're chasing peak efficiency in 5G NR or looking ahead to 6G.
Where it's getting used right now
5G and next-gen wireless
Massive MIMO base stations, O-RAN radio units, small cells, private 5G networks (factories, ports, airports, smart cities), mmWave backhaul. Gen 3 DFE models are especially popular here — they make power amps run cleaner and cooler without burning extra logic.
Massive MIMO base stations, O-RAN radio units, small cells, private 5G networks (factories, ports, airports, smart cities), mmWave backhaul. Gen 3 DFE models are especially popular here — they make power amps run cleaner and cooler without burning extra logic.
Aerospace & defense
Phased-array radars, electronic warfare receivers, SIGINT/COMINT platforms, tactical software-defined radios, satellite links, drone datalinks. High-channel Gen 2 parts (especially ones with SD-FEC) are favorites — reliable and battle-tested.
Phased-array radars, electronic warfare receivers, SIGINT/COMINT platforms, tactical software-defined radios, satellite links, drone datalinks. High-channel Gen 2 parts (especially ones with SD-FEC) are favorites — reliable and battle-tested.
Test & measurement
Vector signal generators & analyzers, wideband spectrum monitoring, high-speed data capture. Need wide instantaneous bandwidth? The 5 GSPS ADC models deliver exactly that.
Vector signal generators & analyzers, wideband spectrum monitoring, high-speed data capture. Need wide instantaneous bandwidth? The 5 GSPS ADC models deliver exactly that.
It's also showing up in medical imaging, cable head-ends, quantum RF chains, industrial multi-sensor systems — basically anywhere people want clean direct RF sampling without a pile of extra components.
Quick “which one should I choose?” guide
I want the most integrated 5G features (DPD, CFR, beamforming acceleration)
→ Pick Gen 3 DFE (ZU65DR / ZU67DR series)
→ Pick Gen 3 DFE (ZU65DR / ZU67DR series)
I need the most DAC channels and fastest output
→ ZU48DR or ZU49DR
→ ZU48DR or ZU49DR
I want good balance — lots of channels + fast ADCs
→ ZU46DR or ZU47DR
→ ZU46DR or ZU47DR
Budget is tight but I still need real RF capability
→ Start with Gen 1 (ZU25DR / ZU27DR)
→ Start with Gen 1 (ZU25DR / ZU27DR)
Harsh environment + strong error correction needed
→ Prioritize models with SD-FEC
→ Prioritize models with SD-FEC
Power & heat are major concerns
→ Choose -2L / -2LI low-power speed grades
→ Choose -2L / -2LI low-power speed grades
Packaging & temperature quick tips
- Need a small footprint? → E1156 (35×35 mm)
- Want maximum I/O pins? → G1517 or larger 42.5 mm packages
- Industrial temp range (-40°C to +100°C) is standard; some low-power grades go up to +110°C
Zynq RFSoC isn't just another FPGA with converters tacked on — it changes how modern RF systems get built. Pick the right member of the family and your design will be smaller, cooler, cheaper to build, and ready for whatever comes next.
Whether you're working on 5G infrastructure, radar prototypes, 6G research, or high-end test equipment, this chip is very likely the heart of your next product.
| Product Attributes | Property Value |
|---|---|
| Manufacturer | AMD |
| Product Series | Zynq® UltraScale+™ RFSoC |
| Packaging | Tray | |
| Part Status | Active |
| Architecture | MCU, FPGA |
| Core Processor | Quad ARM® Cortex®-A53 MPCore™ with CoreSight™, Dual ARM®Cortex™-R5 with CoreSight™ |
| Flash Size | - |
| RAM Size | 256KB |
| Peripherals | DMA, WDT |
| Connectivity | CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART, USB OTG |
| Speed | 533MHz, 1.333GHz |
| Primary Attributes | Zynq®UltraScale+™ FPGA, 930K+ Logic Cells |
| Operating Temperature | -40°C ~ 100°C (TJ) |
| Grade | - |
| Qualification | - |
| Package / Case | 1517-BBGA, FCBGA |
| Supplier Device Package | 1517-FCBGA (40x40) |
| ROHS |  |
Technical Documents
Zynq rfsoc dfe backgrounder
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Zynq9ultrascale 9 rfsoc
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Zynq rfsoc dfe
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Wp509 rfsampling data converters
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Zynq usp rfsoc product selection guide
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Zynq ultrascale rfsoc rf
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Download PDF| Name | Description & Resources | |
|---|---|---|
| ZCU111 RF Data Converter Evaluation Tool |
This evaluation tool consists of reference designs and a custom GUI for the Zynq UltraScale+ RFSoC ZCU111 evaluation board. It not only configures the operation of RF data converters but also evaluates the performance of RF-ADCs and RF-DACs. |
This evaluation tool consists of reference designs and a custom GUI for the Zynq UltraScale+ RFSoC ZCU111 evaluation board. It not only configures the operation of RF data converters but also evaluates the performance of RF-ADCs and RF-DACs. |
|
Evaluation Tool Download | |
| · Evaluation Tool GUI User Guide | · 2021.2 ZCU111 Evaluation Tool | |
| · ZCU111 User Guide | ||
| SD-FEC |
This evaluation tool includes reference designs for the Zynq UltraScale+ RFSoC ZCU208 and ZCU216 evaluation boards, with a custom GUI for configuring RF data converter operations and evaluating RF-ADC and RF-DAC performance. |
This evaluation tool includes reference designs for the Zynq UltraScale+ RFSoC ZCU208 and ZCU216 evaluation boards, with a custom GUI for configuring RF data converter operations and evaluating RF-ADC and RF-DAC performance. |
| Zynq UltraScale+ RFSoC Gen 3 RF Data Converter Evaluation Tool | Evaluation ToolUser Guide | |
| · 2018.3 Design Files | ||
| · 2019.1 Design Files | ||
| · 2019.2 Design Files | ||
|
· 2020.1 Design Files | |
| · Evaluation Tool GUI User Guide | · 2020.1.1 Design Files | |
| · ZCU216/208 User Guide | · 2020.2 Design Files | |
| · 2021.1 Design Files | ||
| · 2021.2 Design Files | ||
| · 2022.1 Design Files | ||
| · 2022.2 Design Files | ||
| · 2023.1 Design Files | ||
| RF Analyzer |
|
The RF Analyzer tool provides a convenient way to configure and debug RF data converters in Zynq UltraScale+ RFSoC devices on any user circuit board. This tool uses a simple GUI to implement debugging functions, enabling seamless interaction with the RF data converter IP example design implemented on the user circuit board. |
|
The RF Analyzer tool is only supported in the Windows environment. | |
| · User Guide | RF Analyzer Download: | |
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· 2020.1 Design Files | |
|
· 2020.1.1 Design Files | |
|
· 2020.2 Design Files | |
|
· 2021.1 Design Files | |
|
· 2021.2 Design Files | |
|
· 2022.1 Design Files | |
|
· 2022.2 Design Files | |
|
· 2023.1 Design Files | |
| Zynq UltraScale+ RFSoC Frequency Planner |
|
The Frequency Planner assists in frequency planning for Zynq UltraScale+ RFSoC devices. |
| RFSoC Frequency Planner Quick Start Guide (v2.1) | RFSoC Frequency Planner Download: | |
|
RFSoC FP installer (2p1 08 07 2023 ) | |
| Getting Started Design |
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Design Files Download: | |
| 2020.2 Design Document - ZCU208 | 2020.2 Design Files- ZCU208 | |
| 2020.2 Design Document - ZCU111 | 2020.2 Design Files- ZCU111 | |
| Zynq UltraScale+ RFSoC Demonstration on ZCU111 using PYNQ |
|
Powered by the ZCU111 evaluation kit, this demonstration implements wireless solutions using PYNQ and Jupyter Notebook. |
| Zynq UltraScale+ RFSoC Demonstration using PYNQ | Zynq UltraScale+ RFSoC Demonstration using PYNQ | |
3rd Gen AMD Zynq™ UltraScale+™ RFSoC Selection Guide
1. Direct RF Signal Chain Features
| ZU42DR | ZU43DR | ZU46DR | ZU47DR | ZU48DR | ZU49DR | ||||
|---|---|---|---|---|---|---|---|---|---|
| Maximum RF Input Frequency (GHz) | 6 | ||||||||
| Decimation/Interpolation | 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, 40x | ||||||||
| 14-bit RF-ADC | Number of ADCs | 8 | 2 | 4 | 8 | 4 | 8 | 8 | 16 |
| 14-bit RF-DAC | Maximum Rate (GSPS) | 2.5 | 5.0 | 5.0 | 2.5 | 5.0 | 5.0 | 5.0 | 2.5 |
| Number of DACs | 8 | 4 | 12 | 8 | 8 | 16 | |||
| Maximum Rate (GSPS) | 9.85* | 9.85* | 9.85* | 9.85* | 9.85* | 9.85* | |||
| SD-FEC | 0 | 0 | 8 | 0 | 8 | 0 | |||
2. Programmable Logic Features
| ZU42DR | ZU43DR | ZU46DR | ZU47DR | ZU48DR | ZU49DR | |
|---|---|---|---|---|---|---|
| System Logic Cells (K) | 489 | 930 | 930 | 930 | 930 | 930 |
| DSP Slices | 1872 | 4272 | 4272 | 4272 | 4272 | 4272 |
| Memory (Mb) | 67.8 | 60.5 | 60.5 | 60.5 | 60.5 | 60.5 |
| GTY Transceivers | 8 | 16 | 16 | 16 | 16 | 16 |
| PCIe Gen3x16 | - | - | - | - | - | - |
| PCIe Gen3x16 / Gen4x8 / CCIX | 0 | 2 | 2 | 2 | 2 | 2 |
| 100G Ethernet MAC/PCS with RS-FEC Support | 0 | 2 | 2 | 2 | 2 | 2 |
| Maximum I/O Pins | 152 | 347 | 360 | 347 | 347 | 408 |
3. Processing System Features
| Description | |
|---|---|
| Application Processing Unit | Quad-core ARM Cortex-A53 MPCore (up to 1.33GHz) |
| Real-Time Processing Unit | Dual-core Arm Cortex-R5F MPCore (up to 533MHz) |
| Embedded and External Memory | 256KB on-chip memory with ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3; External QSPI; NAND; eMMC |
| High-Speed Connectivity | 4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort™ 1.2a; USB 3.0; SGMII |
| General-Purpose Connectivity | 214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real-Time Clock; WatchDog Timer; Tri-state Timer |
- 5G and LTE Wireless
- For wireless infrastructure manufacturers utilizing Zynq RFSoC, it is possible to realize unprecedented reductions in size and power consumption—two critical factors for the deployment of Massive MIMO technology.
- Single-device operation with input/output frequencies reaching up to 7.125 GHz
- Device models featuring integrated LDPC SD-FEC cores and high DSP density, optimized for 5G baseband processing
- Superior millimeter wave IF deployments, including fixed wireless access and mobile backhaul solutions
- Hardened radio digital front-end supporting up to 400 MHz bandwidth (8T8R) for 5G New Radio (exclusive to Zynq RFSoC DFE)
- Remote-PHY for Cable Access DOCSIS 3.1
- The Zynq UltraScale+ RFSoC empowers cable multi-service operators (MSOs) to relocate PHY layer processing to remote PHY nodes near end-users, thereby enhancing overall network capacity.
- RF-Analog technology designed to meet strict power and form factor limitations
- LDPC integration to comply with DOCSIS 3.1 technical specifications
- Expanded spectrum compatibility for DOCSIS 4.0 standards
- FPGA logic enables future-proofing and support for full duplex IP functionality
- Phased Array Radar/Digital Array RADAR
- As a single-chip TRX solution for scalable, multi-functional phased array radar systems, the Zynq UltraScale+ RFSoC delivers low-latency transmit and receive capabilities—essential for fast response times in early warning applications.
- Complete L-Band sampling capability
- Partial direct sampling of S-Band (full S-Band coverage at 2nd Nyquist frequency)
- Partial direct sampling support for C-Band frequencies
- Both software and hardware reconfigurable for flexible deployment
- Test & Measurement
- By leveraging direct RF-sampling, highly adaptable reconfigurable logic, and software programmability in the Zynq UltraScale+ RFSoC, engineers can develop high-speed multi-function instruments for signal generation and analysis.
- Satellite Communications
- Engineers can create high-speed multi-functional test and measurement instruments for signal generation and analysis by utilizing the direct RF-sampling feature, highly flexible reconfigurable logic, and software programmability of the Zynq UltraScale+ RFSoC.
- Success Case: cellXica’s EXSITE®-M5Q® Plus – A Game-Changer for Easy Private 5G Network Deployment
- Company Overview: cellXica, headquartered in Cambridge, UK, is a seasoned player in developing radio equipment, embedded systems, cellular base stations, and wireless communications solutions based on software-defined radio (SDR) technology. With decades of expertise, the company delivers tailored wireless solutions to meet unique connectivity needs across manufacturing, industrial, energy, logistics, and other sectors. Since 2010, it has maintained a track record of innovating high-performance, customized products, supported by advanced adaptive SoC technology.
- Core Challenges: cellXica’s clients face rigorous connectivity demands, often requiring wireless networks to operate in harsh environments like oil refineries, quarries, and mines, as well as traditional settings such as manufacturing facilities and healthcare institutions. These networks need to be highly reliable, low-latency, and capable of covering large or remote areas. Additionally, private 5G deployment requires deterministic performance to support orchestrated industrial workflows, seamless process data collection, system calibration and synchronization, and enhanced worker safety through asset and personnel tracking—all while being more scalable and cost-effective than Wi-Fi alternatives.
- Adopted Solution: To address these needs, cellXica developed the EXSITE®-M5Q® Plus 5G base station, powered by a third-generation adaptive RFSoC—an industry-first single-chip adaptive radio platform. This all-in-one solution integrates 5G radio access network (RAN) and core network functions into a single compact device. The underlying RFSoC combines digital RF signal processing and programmable logic, enabling low-latency, high-throughput communications with minimal size and power consumption. Building on its experience with 3G and 4G base station development, cellXica leveraged the platform’s flexibility to reuse hardware, firmware, and software, streamlining the development of bespoke solutions.
- Key Outcomes:
- Simplified Deployment: The base station supports Power over Ethernet (PoE), eliminating the need for additional servers, power cabling, or complex infrastructure—clients only require an Ethernet cable for setup.
- Exceptional Performance: Equipped with a 4x4 MIMO radio architecture (1 watt per antenna port) operating on n77 and n78 bands, it delivers up to 450 Mbps throughput, telco-grade low latency, end-to-end security, and centralized device management.
- High Scalability: It adapts to diverse use cases, including standalone single-cell coverage, multi-cell networks for large premises, and geographically distributed networks securely connected via the public internet.
- Smooth Technology Migration: Leveraging a stable, reusable codebase, cellXica achieved seamless transitions from 3G to 4G and ultimately to 5G—preserving testing history and maintenance efforts, which would have been challenging with traditional ASIC solutions. This accelerated time-to-market and maintained competitive advantage.
- Customer Perspective: Niro Mahasinghe, CEO of cellXica Ltd., noted, “Our all-in-one design is unique—we’ve integrated the radio, base station baseband processing, and 5G core network software into a single Arm® processor complex. While others have tried this with dedicated chipsets, the programmable logic fabric of our chosen RFSoC lets us adopt the latest standards much faster. We’ve extended the value of prior investments through codebase continuity, making innovation for our customers a far smaller step than starting from scratch.”
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